ByAdan Flannigan 2019-06-24 2056
We found a very interesting thing: The internal CPU does not consist of a large core, but is divided into a CPU core and E / A. The core consists of two parts, the CPU core, which is built in the 7 nm process, while the E / A core is built in the 12 nm process. The memory controller is no longer integrated in the CPU core, but is removed to the E / A core. Data exchange with the CPU core via the Data Fabric Bus.
In fact, not only the data controller of the E / A core is used for data exchange between the memory controller and the CPU, but the PCI-E controller, which provides the PCI-E 4.0 channel, is also integrated into the E / A core. Direct data exchange between CPU, memory and GPU takes place via the Data Fabric Bus. Do you think this structure is a little familiar? Yes, at this point the E / A core of the processor actually corresponds to the Northbridge chip on the motherboard a long time ago. It's the data exchange center for the entire platform, so we can even say that the third generation Ruilong desktop processor is the whole thing. The platform seems to have returned to the structure "CPU + North Bridge + South Bridge" a long time ago.
Why does AMD use this seemingly backward structure in its latest desktop processor? In this context, we might want to take a look at the memory controller development process to find out what advantages and disadvantages the memory controller has at different locations. Perhaps we can better understand why AMD belongs to the third generation of the Ruilong desktop Plug the memory processor in the processor into the E / A core.
Before AMD's K8 architecture processor and Intel's core processor debut, the two CPU platforms are the most traditional "CPU + North Bridge + South Bridge" structure. The CPU is a pure CPU at this time and has no other functions than the arithmetic instructions. The North Bridge chip is the data exchange center of the entire motherboard and integrates the memory controller and the AGP / PCI-E controller, as well as other important control functions. It is used to expand peripheral I/O interfaces such as SATA and USB interfaces.
During this time, the Northbridge chip determines what type of memory and graphics card the motherboard can support. The Southbridge chip determines how many peripheral E / A interfaces the motherboard can provide. At that time, many motherboards were divided into markets by their Northbridge chips, and the name of the product model was also inserted into the Northbridge chip name to underline the positioning of the products. This architecture also gives the platform a high degree of flexibility: by combining different Northbridge and Southbridge chips, manufacturers can further divide the product line, while the old CPU can also be retained by using it on the new motherboard. New features such as the Intel Pentium E5200 processor support DDR2 memory in conjunction with the P965 motherboard and DDR3 memory in conjunction with the P45 motherboard.
However, this structure has the disadvantage that the load of the North Bridge chip is too high: Since the data exchange of the entire platform must take place via the North Bridge chip, the database width of the North Bridge chip must be sufficient to meet the requirements of the entire platform. With the increasing demand for CPU, memory and graphics performance in different applications, the data exchange rate between the three is accelerating. This traditional architecture is overwhelmed, especially between CPU and memory. Data exchange, the bus bandwidth between the Northbridge chip and the CPU is becoming increasingly difficult to satisfy, and to some extent this also restricts the performance of the CPU, at which point a new structure is required to meet the performance requirements of the entire platform.
From AMD's perspective, memory controllers were integrated into desktop CPUs earlier than Intel, in the era of the K8 architecture processor, and Intel's platform was still in the traditional north-south bridge structure. AMD has thus reached a technical level of counterattacks. The biggest advantage of integrating the memory controller into the CPU is that the data access delay between the CPU and memory is greatly reduced and the operation of both is nearly synchronized, so that the performance of the CPU core can be fully maintained. Play.
Because the North Bridge chip has stripped the memory controller, its load can be described as greatly reduced, reducing its own size, power consumption and heat generation. However, since it also has to assume the function of the PCI-E controller, the northbridge chip is still an important criterion for distinguishing the motherboard level at this point, but at least the memory that the motherboard can support is no longer determined by the northbridge chip. The difference between the notes on the motherboard is reduced to some extent.
Intel first integrated the memory controller into the CPU with the first generation of core processors and simultaneously started the core processor with the familiar i3 / i5 / i7 level. However, AMD continues to maintain the North and South Bridge motherboard chipset after the memory controller is integrated: The first generation of core processors with the exception of the Core i7-9xx series of the X58 platform only needs to be equipped with a motherboard chip, because Intel not only integrates the memory controller into the CPU, but even the PCI-E controller has been integrated into the CPU (the Core i7-9XX series does not have an integrated PCI-E controller), so the CPU at this time like "CPU +" is the combination of the North Bridge, but since some of the functions of the original Northbridge chip still require the motherboard chip, this time the motherboard chip is not only the South Bridge, but more than the traditional South Bridge chip.
The "integration" of the first-generation core processor, however, does not consist of combining all components in a single core. In fact, the first generation core processor, based on the 32 nm process and the Clarkdale core, is actually divided into CPU + GPU. A separate core, the CPU core, continues to provide pure computing, while the memory controller and PCI-E controller are located in the GPU core, but the distance between the two is greatly reduced and internal routing can also be maintained. The best optimization, i.e. still a significant increase in overall performance.
In contrast, AMD, although it integrates the memory controller in the CPU from the K8 architecture, but up to the bulldozer, stack driver architecture CPU, it still does not integrate the PCI-E controller in the CPU, therefore, from the structure of the entire motherboard It is still the traditional "CPU + North Bridge + South Bridge" design, which poses some difficulty for the manufacture of the motherboard and is not conducive to further improving the overall performance of the machine.
After easily integrating the first generation CPU + North Bridge core processors, Intel has integrated the memory controller, PCI-E controller and core graphics card into a second generation core processor core. Of course, in order to distinguish between the different motherboard chips, some of the platform functions still have to be compared with the corresponding motherboard chips: For example, only the P Series and Z Series motherboards can support overclocking of the K Series processor, while the P Series motherboards cannot support the core display. Output and more.
Although AMD in the first generation of the AVerMedia processor must integrate the main functions of the Northbridge chip into the CPU, its APU has already realized the corresponding technology earlier. It can be seen that it has a complete "CPU + GPU + North Bridge" function and the three are combined in a core, whereby with a high degree of integration the corresponding motherboard platform has thus changed from "chipset" to "chip". From here we can also see that AMD cannot technically integrate the Northbridge chip into the CPU, but for various reasons and needs only with the introduction of the first generation of the Acer processor. Just design.
Now we look back at the third generation Ruilong desktop processor, which in its current structure uses a similar structure to the first generation Intel Core processor, namely the CPU core and the E / A. The core (equivalent to the traditional Northbridge core) is packaged separately and then integrated into a printed circuit board. Theoretically, such a structure is not conducive to data exchange between the CPU core and the memory controller, even if there is a higher memory latency on the same board than during integration into the CPU core. And we can also see that if it is a product with more than 8 cores, the two CCDs want to exchange data, this must be done via the Data Fabric bus on the E / A core. This is not a good performance to improve CPU performance. Design. From this point of view, we can even say that the third generation Athlon processor is a bit like a review.
Why does AMD adopt this turnback design? AMD said that all designs are actually being considered. In fact, no part of these designs can be separated separately. You have to look at the design of the whole CPU. There is no denying that this structure is not a CCD. The best design for data exchange between modules is not the best communication method between the CPU core and the memory controller. However, after considering various aspects of performance comprehensively, the balance of this design is best, first with the internal CPU. The large cache design and command prediction mechanism of the Zen 2 architecture have largely solved these problems, and the final CPU performance can explain everything.
Secondly, this is a highly flexible structure: With a different number of CCD cores and E / A cores, different product levels can be easily derived, for example processors with 8 cores and 16 threads. A CCD module can be used, or one of the CCD modules can be replaced by a GPU, and then the corresponding APU product can be derived. In addition, this modular design does not affect the operation and performance of other modules after one of the modules has been replaced or removed, making it easier to set up the CPU or APU.
To take a step back, the current 7nm process is still a new process for AMD, and both capacity and maturity are in an upward phase. During this time, the capacity allocation was to be optimized and the most important components placed on the 7 nm process. The rest of the process uses a more mature 12nm process that also helps improve product yield, which in turn increases effective capacity and allows players to feel the power of the new architecture processor.
Will the future Zen 2 architecture have more integrated products? AMD hasn't revealed it, but the possibility is still very great. For example, if the 7nm process is mature and capacity is very sufficient, the CPU and APU of the Zen 2 architecture are likely to return to fully integrated design. If there is such a time, will the Zen 2 architecture still deliver higher performance? Maybe you'd like to wait and see.
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