ByMorris Kovach 2020-02-19 196
Recently, at the International solid State Circuits Conference (ISSCC 2019) in San Francisco, Toshiba announced the development of a bridge chip that can achieve high-speed and high-capacity SSD. Compared with the traditional bridgeless chip method, by using the newly developed bridge chip with small area and low power consumption, we can successfully connect more flash chips with fewer high-speed signal lines.
In SSD, the master needs to connect multiple flash particles to control data storage, but with the increasing number of flash particles, the data transmission speed of SSD will slow down, so the connected flash particles are limited. In order to increase the capacity, we not only need to increase the number of interfaces, but also connect more high-speed signal lines to the main control, which also increases the difficulty of PCB wiring of SSD.
Toshiba has overcome this problem by developing a bridge chip that connects master and flash memory particles, including three new technologies: ring daisy chain connection, serial communication using PAM 4, and jitter improvement technology to eliminate the jitter of PLL circuits in the bridge chip.
The ring configuration of daisy chain connection reduces the number of transceivers needed for bridging chips from two pairs to one pair, so that the chip area is reduced, and PAM 4 is used for serial communication between the main control chip and the bridging chip, which reduces the operation speed of the circuit in the bridging chip and reduces the performance requirements of the transceiver. The use of a new CDR circuit with PAM 4 characteristics can improve the jitter characteristics and eliminate the need for the PLL circuit of the bridge chip, thus reducing the area of the bridge chip and reducing the power consumption.
Through the use of these technologies, the overhead of bridging chips is reduced, and only a small number of high-speed signal lines can be used to enable the master to operate a large number of flash chips at high speed. The prototype bridge chip is built by 28nm CMOS process, and the result is evaluated by connecting four bridge chips and the master in the ring daisy chain. All bridging chips and master controllers can achieve satisfactory performance under PAM 4 communication under 25.6Gbps, and the BER (bit error) is less than 10 ^-12.
Toshiba will continue to further improve the performance of bridge chips, reduce area and power consumption, and achieve unprecedented high-speed and high-capacity storage. Perhaps with the blessing of this technology, the future SSD will be able to achieve faster speed and larger capacity using mid-and low-end master controls, which is also an invisible technology that benefits consumers.
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